An integrated circuit die is a small device formed on a semiconductor wafer, such as a silicon wafer. Such an integrated circuit die is typically singulated from the wafer and attached to a substrate or base carrier for redistribution of electrical interconnects. Bond pads on the integrated circuit die are then electrically connected to the leads on the leadframe via wire bonding or solder bumps. The integrated circuit die and the leadframe are encapsulated with a protective material such that a package is formed. The leads encapsulated in the package are redistributed in a network of conductors within the carrier and end in an array of terminal points outside the package. The terminal points allow the integrated circuit die to be electrically connected with other circuits, such as on a printed circuit board.
Modern consumer electronics particularly personal portable devices, such as cell phones, digital cameras, music players, PDA's, and location-based devices, require miniaturization as well as increasing integrated circuit die content to fit an ever shrinking physical space. Numerous technologies have been developed to meet these requirements. Some of these technologies involve flip chip integrated circuit die in integrated circuit packages. The demand for flip chip packages for integrated circuit die applications is increasing. These technologies have struggled with manufacturing and fabrication problems including the attachment of the integrated circuit die and its electrical connection. Other problems include stresses, fatigue, delamination and contamination often resulting in damage to the integrated circuit die. This damage causes failures that are sometimes intermittent and hard to detect or analyze. Broad use of flip chip integrated circuit die has extended the needs for reliability and performance beyond even recent expectations.
With the continual miniaturization of electronic components and overall systems, the solder bump becomes smaller as well. This reduction in the size of the solder bump places increasing demands on the mechanical properties of the solder to ensure joint robustness. In addition to footprint reduction, there is an emphasis on total space reduction, often leading to reduced size in the packaging of the silicon die. As surface mount technology migrates toward smaller package dimensions, the physical and thermal characteristics of each packaging material become more critical. Differences between materials within a package from layer to layer or between the leadframe and the die can cause internal stresses also placing demands on the packaging materials.
Thus a need still remains for an integrated circuit package system to ensure that the manufacturing methods provide increasing reliability and performance. In view of the ever-increasing need to save costs and improve efficiencies, it is more and more critical that answers be found to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.